1. Field of the Invention
The present invention relates to a semiconductor circuit structure. More particularly, the present invention relates to a circuit structure which avoids a latchup effect.
2. Description of the Related Art
A complementary metal oxide semiconductor (CMOS), a basic semiconductor device, comprises a P-type metal oxide semiconductor (PMOS) and an N-type metal oxide semiconductor (NMOS). The CMOS consumes less power and the speed of the CMOS is as fast as the NMOS, so that the CMOS is widely used to fabricate high-integration devices.
FIG. 1 is a schematic, cross-sectional diagram of a conventional CMOS. FIG. 2 is a schematic circuit diagram of the CMOS in FIG. 1. The same component in FIGS. 1 and 2 is indicated by the same numeral.
Referring to FIGS. 1 and 2, an N-well 102 is in a P-type substrate 100. A PMOS 104 is on the N-well 102 and an N-type contact 108 is in the N-well 102. A P-type contact 110 is in the P-type substrate 100 and an NMOS 106 is on the P-type substrate 100. A gate of the PMOS 104 and a gate of the NMOS 106 connect to an input terminal 112. A drain region of the PMOS 104 and a drain region of the NMOS 106 connect to an output terminal 114. A source region of the PMOS 104 and the N-type contact 108 connect to a voltage source 116. A source region of the NMOS 106 and the P-type contact 110 connect to a ground terminal 118.
When a voltage of the input terminal 112 is "High", the NMOS 106 is ON and the PMOS 104 is OFF. Therefore, a voltage of the output terminal 114 is about equal to the ground terminal which is about V.sub.ss. When the voltage of the input terminal 112 is "Low", the NMOS 106 is OFF and the PMOS 104 is ON. The voltage of the output terminal 114 is about V.sub.dd which is about equal to the voltage source 116.
However, a parasitic bipolar transistor is easily formed in the CMOS. For example, in FIG. 1, a vertical, PNP-type bipolar transistor (not shown) is formed by the drain region of the PMOS 104, the N-well 102 and the P-type substrate 100. Two horizontal, NPN-type bipolar transistors (not shown) are formed respectively by the source region and the drain region of the NMOS 106, the P-type substrate 100 and the N-well 102. A positive feedback loop (not shown) is formed by these two bipolar transistors. Furthermore, these two bipolar transistors connect to each other in a structure similar to a PNPN-type diode as shown in FIG. 3.
While operating the CMOS, if a current passes through the PNPN-type diode that is larger than a triggering current of the PNPN-type diode, the PNPN-type diode is activated. A low resistance current path (not shown) is established between the voltage 116 and the ground terminal 118 at this time, so that massive current flows in this current path. This means that current leaks from the N-well. The function of the CMOS temporarily or permanently fails. This is known as a latchup effect, and occurs during CMOS operation.